1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor integrated circuit with a high degree of integration
2. Description of the Background Art
A method of manufacturing a bipolar transistor on a semiconductor integrated circuit substrate was discussed in detail in the Latest LSI Process Technology, Apr. 25, 1984, published by Industrial Board of Inquiry.
FIG. 1 shows the configuration of the bipolar transistor disclosed in above literature. This bipolar transistor comprises: a collector region 94 which is an island formed in an N-type epitaxial layer 91 from a lower isolating region 92 and an upper isolating region 93; a P-type base region 95 formed within the island; and an N.sup.+ -type emitter region 96 formed within the base region 95. This type of bipolar transistor is manufactured by a process comprising steps of:
(i) forming a SiO.sub.2 film on a P-type semiconductor substrate 90, forming a doping window for the buried layer 92 in the SiO.sub.2 film, and selectively doping the P-type semiconductor substrate 90 with antimony through the doping window;
(ii) forming an SiO.sub.2 film again on the P-type semiconductor substrate 90, forming a doping window for the buried layer 98 in this SiO.sub.2 film, and selectively doping the semiconductor substrate 90 with boron through the doping window;
(iii) growing the epitaxial layer 91 on the surface of the semiconductor substrate 90, followed by forming an SiO.sub.2 film on the surface of the epitaxial layer 91;
(iv) forming a doping window for the upper isolating region 93 in the SiO.sub.2 film on the surface of the epitaxial layer 91 and selectively doping the epitaxial layer 91 with boron through the doping window;
(v) heat-treating the semiconductor substrate 90, and diffusing the various regions which were doped in the foregoing steps simultaneously, linking the lower isolating region 92 and the upper isolating region 93;
(vi) forming a doping window for the base region 95 in the SiO.sub.2 film on the surface of the epitaxial layer 91, selectively doping the epitaxial layer 91 with boron through the doping window to form the base region 95;
(vii) forming doping windows for the emitter region 96 and for a collector contact region 97 in the SiO.sub.2 film on the surface of the epitaxial layer 91, and doping the epitaxial layer 91 with phosphorous (P) through the doping windows to form the emitter region 96 and the collector contact region 97; and
(viii) forming openings in respective portions of the SiO.sub.2 film for the base region 95, the emitter region 96, and the collector contact region 97 to form each contact window, and applying aluminum to the surface of the semiconductor substrate 90 by evaporation to form respective aluminum electrodes which extend to the surface of the SiO.sub.2 film from the base region 95, the emitter region 96, and the collector contact region 97.
As outlined above, in a method of manufacturing a semiconductor integrated circuit wherein the upper isolating region 93 and the lower isolating region 98 are diffused simultaneously from the upper and lower surfaces of the epitaxial layer 91 respectively to form the isolating regions, the area occupied by the upper isolating region 93 of the epitaxial layer 91 is small compared to that obtained by other methods of manufacturing a semiconductor integrated circuit wherein the isolating regions are formed by diffusion from the top surface of the epitaxial layer only, and a comparatively high degree of integration is achieved.
However, when designing the depth of diffusion of the upper isolating region 93, for example, 10 .mu.m, the upper isolating region 93 also extends to the same extent in the lateral direction, so that the spacing between the upper isolating region and each region must be over 12 .mu.m which is a sum of the diffusion distance (10 .mu.m) of the upper isolating region 93 and a spacing margin (2 .mu.m). For this reason, even with the above described method of manufacturing a semiconductor integrated circuit, the high degree of integration desired today in a semiconductor integrated circuit is not adequately obtained.
Because the upper isolating region 93, the base region 95, and the collector contact region 97 formed in the fourth, sixth, and seventh steps are selectively doped through different SiO.sub.2 films, there is concern that the positions which these regions occupy will deviate from the design values, as shown by the dotted lines in FIG. 1, because of the mask alignment required to form the doping windows in each SiO.sub.2 film or for the subsequent etching. For this reason, the spacing of these regions must be designed to provide a preset allowance so that contact between these regions resulting from the diffusion treatment is avoided. This is a hindrance to high integration. Also, in step 8 in which the respective contact windows in the SiO.sub.2 films for the base region 95, the emitter region 96, and the collector contact region 97 are formed, the contact windows in the base region 95 and the emitter region 96 are completed prior to completely opening the window in the collector contact region 97 because the SiO.sub.2 film for the base region 95 is comparatively thinner than the SiO.sub.2 film for the collector contact region 97. The problem exists that side etching will proceed even further and these contact windows will be expanded beyond the design value. Therefore, it is difficult to design an extremely small base region, and this is a hindrance to high integration in a semiconductor integrated circuit. Also, depending on the etchant used at this time, when the base region 95 and the emitter region 96 are etched the production yield is poor.